OVP Technology enabled in OSCI TLM2.0

Over recent months there has been much talk of how TLM2.0 enables SystemC to become the glue for putting platforms together using models written in C, C++, or SystemC. Many people interested in the high speed models of OVP, especially the certified processor models, requested that we see if OVP models could work efficiently within a SystemC TLM environment.

In OVP, models have bus interfaces that are transaction oriented. We spent time reviewing TLM2.0 so we could understand how to make OVP fast models best work in this TLM 2.0 infrastructure.

We have completed that work and all OVP processor models now come with a TLM2.0 interface layer (wrapper) enabling them to be used natively in SystemC TLM2.0 platforms. OVP peripherals can also have a wrapper layer to enable their use in SystemC TLM 2.0 platforms. We have completed several examples of 'wrapped' peripherals and these are part of the standard OVP release.

We are very pleased with the result and now any SystemC TLM2.0 user can access OVP processor models of ARM, MIPS, ARC, NEC v850, PowerPC, and OR1K processors running 500-1,000 MIPS. The fastest recorded speed on a 2.8GHz desktop PC is a MIPS 32 bit RISC running the peakspeed2 benchmark at 2,200 MIPS (yes over 2 Billion Instructions Per Second!).

Thank you to the many companies and individuals from the following entities that agreed to review our beta code and to those that provided valuable feedback:
Analog Devices, Cadence, Doulos, Elda, EVE, Forte, GreenSocs, HCL Technologies, IIT Delhi, Imperas, Intel, Posedge Software, University of Lugano.

Background

OSCI TLM2.0 is a layer for interoperability between memory mapped bus models. There is a generic payload with extension mechanism, an API for memory mapped bus modeling, and there can be loosely-timed and aproximately-timed modeling.

Loosely-timed is the higher performance of the two timing models and enables processes to run ahead of simulation time (temporal decoupling) and uses a 'quantum keeper'. Transactions can use a blocking transport interface and can include timing annotation.

There is also a Direct Memory Interface (DMI). This gives the initiator a direct pointer to memory in the target and bypasses the sockets in normal transport calls. There are extensions for security modes and the target can invalidate the DMI pointer if needed.

OVP Approach to TLM2.0

The goal of the TLM2.0 OVP integration is to provide OVP CPU models that work in SystemC platforms as fast as possible.

Our approach is to provide wrappers of all OVP CPUs and all OVP peripherals.

The OVP solution allows memory to be instantiated in the OVP subsystem or outside the OVP subsystem as SystemC memory. The TLM2.0 DMI capability can be used, and OVP CPU models initiate a DMI negotiation by default.

The use of memory in the OVP models is required for efficient SMP, CMP, shared memory, and, sparse memory systems - please read more in the OVP documentation regarding this.

For convenience we have also provided variants of a TLM2.0 bus decoder and memory model.

Examples of different OVP TLM2.0 platform configurations

Details of OVP inside TLM2.0

There is a generic wrapper that is put around all OVP CPU models. This wrapper is used in a processor configuration specific layer which is then instanced into the SystemC platform. The wrappers do not have separate data and instruction buses - this could be added. The wrappers do support interrupts and allow control of all model features using configuration attributes.

The CPU models automatically use DMI by default - meaning that they negotiate the best possible performance with the memory subsystem.

Behavioral and Peripheral models can be bus master or slave and work with interrupts. Automatic DMI has not been implemented in the behavioral model wrappers (if you need this in your bus mastering peripheral please contact us for examples).

There is a global quantum implemented and time is synchronized between OVP cpu models, peripheral models and SystemC time.

With the TLM2.0 wrappers we have not implemented the standard OVP features of dynamic bus mapping and memory invalidate.

TLM2.0 with OVP Summary

OVP is providing a rich set of open source processor models, that currently include ARC, ARM, MIPS, and OR1K processor families. These are fast, free, and easy to use.

TLM2.0 can be used as glue to stick models together to create virtual platforms using SystemC.

With the OVP TLM2.0 support, it is easy to use OVP model within TLM2.0 platforms to gain performance.

OVP TLM2.0 Model Download

Please visit the download TLM2.0 page to download the models and wrappers so that you can use them with your SystemC platforms.

If you want to read the user guide that explains how OVP models are used within TLM2.0 platforms, read the OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf document.

Please download the OVPsim package and look in the Examples directory for some self contained SystemC TLM2.0 platforms that show the source of how to use these OVP models in your TLM2.0 platforms.

Also, please look in the OVPsim package's demo directories for some self contained demonstrations of the OVP TLM2.0 integration running different benchmark simulations.

If you require further information, please have a look at the forums and post a question, or email us.