New release includes MIPS-Based SystemC TLM-2.0 Reference Platform

THAME, United Kingdom, June 22, 2010 – Imperas, which through the Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, today announced a major release of new technology. Highlights of this June 2010 release are the virtual platform simulator OVPsim, which has improved its industry leading performance by 50 percent; fast models of PowerPC processors, and a MIPS-based reference platform under SystemC/TLM-2.0 which boots both Linux and Mentor Graphic’s Nucleus RTOS.

OVPsim, which for basic instruction set simulation of processors achieves over 2 billion instructions per second (or over 2,000 MIPS), achieves hundreds of MIPS performance for real world virtual platforms. ARM and MIPS-based virtual platforms can boot Linux in less than 5 seconds on a 2GHz laptop with OVPsim.

“Virtual platforms are providing significant benefits to our software team, as they make it easier to maintain existing software and develop new applications for existing avionics systems” said Dan Radke, USAF, 559th Software Maintenance Squadron. “Key attributes of virtual platforms are realizing far greater speed of software simulation, especially for multiprocessor systems, having more standard approaches to develop models to, and being able to use open source models of processors and peripherals already available, making it easier for us to build our own efficient models of complete avionics systems.”

The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.

“The first questions from our customers are always about simulation speed and model availability,” said Umesh Sisodia, founder and CEO of CircuitSutra. “Even before this release, OVP made it easy to answer those questions, but these additions to OVP for simulation speed, additional models and the TLM-2.0 reference virtual platform make OVP even easier to use and adopt.”

Reference virtual platforms provide a known good starting point for users looking to develop their own virtual platforms. OVP has released a reference virtual platform of the MIPS Malta board, running under SystemC/TLM-2.0, that boots either Linux or the Mentor Graphics Nucleus RTOS. This virtual platform can be used to understand the operating systems, since the virtual platform simulation can provide more visibility and controllability than just executing and debugging on the hardware itself. The virtual platform can also be used for the development of applications running under Linux or Nucleus on a MIPS-based system. Moreover, the virtual platform is open source, and it’s easy to add peripherals to the virtual platform using SystemC/TLM-2.0 models and develop drivers for those peripherals.

“Our licensees are focused on speeding time-to-market and extracting the highest possible performance from their SoCs,” said Art Swift, vice president of marketing for MIPS Technologies. “Virtual platforms give users a head start in the development cycle. Having a virtual platform of a common development board running at real time speeds can potentially shave weeks or months off of a typical development cycle.”

“We founded OVP 2 years ago to provide the infrastructure technology – simulation and models – to the embedded software community,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Over this time we’ve seen the community – users, tool developers, processor IP vendors, service providers, academia – come together around OVP to help them with embedded software development. We’re proud and excited to be part of this industry momentum, and to continue to contribute to OVP.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Open Source Models Available Now for Free on OVP Website

THAME, United Kingdom, June 8, 2010 – Imperas, which through the Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, today announced the release of fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching over one thousand million instructions per second (MIPS). The models are free and available as open source from the OVP website.

The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.

“The Power Architecture is an important embedded processor family,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Users have been asking for fast models of the PowerPC processor cores, and we’re now able to deliver these models, open source and free, through Open Virtual Platforms. This is just a continuation of the momentum in the OVP initiative.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.
Fast Instruction accurate models are available from the OVP website for MIPS, ARM, Virage ARC, NEC v850, Power Architecture, OpenCores, SPARC and other processor families.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Mentor Graphics Nucleus RTOS Running on ARM and MIPS-Based Free Reference Platforms Available Through Open Virtual Platforms (OVP)

THAME, United Kingdom, May 24, 2010 – Imperas today announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded™ software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.

The initial result of this flow is the release of free reference virtual platforms by Imperas based on ARM and MIPS processor cores, running the Mentor Nucleus RTOS. These reference virtual platforms are available from the Open Virtual Platforms (OVP) website, www.OVPworld.org/Nucleus. The reference virtual platforms constructed from OVP open source models make it easy for embedded systems developers to use these platforms as a starting point for building their own virtual platforms. A compiled version of the Mentor Nucleus RTOS running on the reference platforms is available for demonstration. Developers interested in using the Nucleus product will need to get a license from Mentor.

“Embedded software is the key differentiator for today’s products and we need to make it easier for people to develop embedded systems,” said Glenn Perry, general manager of Mentor Graphics Embedded Software Division. “Virtual platforms are one way to accelerate software development, and we are excited that Imperas has provided a flow that enables users to run Nucleus RTOS and EDGE on OVP reference platforms.”

A virtual platform is a set of models and a simulation engine that enables the same software binaries that would run on the hardware to be executed on a software, or virtual, platform. Because instruction-accurate models do not require the full implementation details of the hardware, they can be more easily and quickly developed, enabling software development to start months before any hardware is available. In addition, software development on virtual platforms offers the benefit of simulation of any system: full visibility and controllability, unlike the limited access that hardware provides as a software development environment. Further benefits of virtual platforms include real-time simulation speed of hundreds of millions of instructions per second, and deterministic behavior, enabling simulation runs to be repeated.

“Just as we cannot imagine developing hardware without using simulation, software simulation, or virtual platforms, are moving into the mainstream of embedded software development for SoCs (systems on chips),” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Making it easier to get started with virtual platforms by releasing reference platforms with the most popular operating systems such as Nucleus RTOS provides great value to the OVP and embedded systems communities.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Mentor Graphics and Nucleus are registered trademarks and Mentor Embedded is a trademark of Mentor Graphics Corporation. MIPS, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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Fast Models Developed Under MIPS-Verified™ Program

THAME, United Kingdom, March 31, 2010 – Imperas today released models of the new MIPS32® M14K™ and M14Kc™ processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPSTM code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified™ program.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS/M14K. The models of the MIPS® processor cores, as well as models of the other MIPS processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

“The M14K cores and the microMIPS ISA represent groundbreaking technology for microcontrollers and other low footprint embedded applications, where performance requirements together with cost and silicon size limitations are driving our customers,” said Sandeep Vij, president and CEO, MIPS Technologies. “Having MIPS-Verified support from Imperas and OVP, the leading independent supplier of fast models of processor cores, enables our customers to get started immediately with designs leveraging M14K cores.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. The OVP simulator also has an Eclipse IDE integration, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“Complex systems and performance and quality requirements demand that developers have state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP was founded to enable users to have fast simulation and other tools for software development, thus accelerating the development cycle.”

OVP offers MIPS developers access to the M14K models, as well as access to models of other MIPS processors, including the MIPS32 4K®, 24K®, 34K®, 74K® and 1004K™ families of cores. OVP also has reference virtual platforms incorporating the MIPS cores, including bare metal platforms and a virtual platform of the MIPS Malta™ development board. This Malta virtual platform enables users to boot Linux in under 5 seconds on a 2GHz laptop using OVPsim. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

MIPS, MIPS32, M14K, M14Kc, 4K, 24K, 34K, 74K, 1004K, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
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OVP Continues to Build Momentum as the De Facto Source of Fast Processor Models

THAME, United Kingdom, March 23, 2010 – The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605. Additionally, Virage Logic and Imperas have cooperated on the verification of the functionality of the models. Virage Logic’s ARC line of processor cores, the world’s second most widely used processor architecture, are commonly used in audio and video subsystems, and in flash controllers, among other applications. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching hundreds of millions of instructions per second. The models are free and available as open source from the OVP website.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models.

“Imperas is moving the embedded systems industry forward with its visionary approach to virtual platforms and the easy accessibility of OVP,” said Dr. Yankin Tanurhan, vice president and general manager, processor and NVM solutions, for Virage Logic. “Verifying the compatibility and functionality of these high-performance models of our ARC processors and making them freely available is a huge advantage for design teams worldwide. This availability will help enable them to develop high-quality software faster and more easily using virtual platform models of their complete SoCs and embedded systems.”

“As the semiconductor industry’s trusted IP partner, Virage Logic recognizes the importance of freely available models to enable rapid growth and accelerate the design and programming of embedded systems on chip,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Compatibility and quality of models is essential when using virtual platforms to develop software. Offering free, verified processor models means developers can get higher quality software developed faster and help close the software gap.”

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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