OVP Support for Tensilica Processors

This page is dedicated to the Tensilica processors.

To read the Press Release about the relationship with Tensilica click here.

On the right you will see the different downloads available related to Tensilica processors - from simple single processor platforms running benchmark applications through to multi-core examples.

You can use Tensilica processor models obtainable from Tensilica within OVP simulations. This is accomplished by 'wrapping' the Tensilica processor model with an 'integration adaptor' to encapsulate it and make it appear to an OVP platform as a normal OVP processor model.

Using the OVP encapsulated Tensilica processor model

To use the Tensilica model you will need several things downloaded. You will need to download a) the OVPsim simulator, b) the Tensilica model itself, and c) if you don't already have the toolchain to compile up Tensilica applications, you will need that too... And then take a look at some of the examples - they provide pointers as to what is needed for starter platforms. Then you will need to write your own platform.c file, application.c and when compiled - you will be all set.

Where are the platforms and wrappers?

The example platforms are now part of the normal OVPsim download and once OVPsim is downloaded and installed you will find them in the Examples\Vendors\Tensilica directory.

The Tensilica Diamond Core encapsulation or wrapper is now part of the normal OVPsim download and once OVPsim is downloaded and installed you will find it in the lib\Windows\ImperasLib\imperas.com\processor\diamondCore directory.

What Tensilica Diamond Cores are supported?

To list the currently supported Diamond Cores, please visit the Tensilica Diamond Core page in the libary.

Tensilica Demo Slide Presentation

Not Yet Available (June08).

Tensilica Demo Video Presentation

Not Yet Available (June08).

Tensilica Diamond Encapsulation Platform Examples

OVP Encapsulation of Tensilica Diamond Core Processors, associated examples.

Tensilica Diamond Core integration with OVPsim (0.1 MB)
Using Tensilica Diamond Cores within an OVPsim platform. Instancing just like native OVP processor models.

OVPsim Fast Free Simulator

Just-In-Time Code Morphing simulator that runs OVP models up to 500 MIPS for embedded software development.

OVPsim (9 MB)
Binary of the simulator, headers, examples of creating processors, peripherals and platforms, and running. Full Documentation. Current version 20080815.0